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www.irf.com 1 3-phase-bridge driver product summary description packages the irs233(0,2)(d)(s & j) is a high voltage, high speed power mosfet and igbt driver with three independent high and low side referenced output channels. proprietary hvic technology enables ruggedized monolithic construction. logic inputs are compatible with cmos or lsttl outputs, down to 3.3 v logic. a ground-referenced operational amplifier provides analog feedba ck of bridge current via an external current sense resistor. a current trip function which terminates all six outputs is also derived from this resistor. an open drain fault signal indicates if an over-current or undervoltage shutdown has o ccurred. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. propagation delays are matched to simplify use at high frequencies. the floating channel can be used to drive n-channel power mosfet or igbt in the high side c onfiguration which operates up to 600 volts. absolute maximum ratings features ? floating channel designed for bootstrap operation fully o perational to +600 v ? tolerant to negative trans ient voltage ? dv/dt immune ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for all channels ? over-current shutdown turns off all six drivers ? independent half-bridge drivers ? matched propagation delay for all channels ? 3.3 v logic compatible ? outputs out of phase with inputs ? cross-conduction prevention logic ? integrated operational amplifier ? integrated bootstrap diode function (irs233(0,2)d) ? rohs compliant may 8, 2008 irs233(0,2)(d)(s & j)pbf v offset 600v max. i o+/- 200 ma / 420 ma v out 10 v ? 20 v (233(0,2)(d)) t on/off (typ.) 500 ns deadtime (typ.) 2.0 us (irs2330(d)) 0.7 us (irs2332(d)) 28-lead soic 44-lead plcc w/o 12 leads typical connection applications: *motor control *air conditioners/ washing machines *general purpose inverters * micro/mini inverter drives
www.irf.com 2 irs233(0,2)(d)(s&j)pbf qualification information ? industrial ?? qualification level comments: this family of ics has passed jedec?s industrial qualification. ir?s consumer qualification level is granted by extension of the higher industrial level. soic28w msl3 ??? , 260 q c (per ipc/jedec j-std-020) moisture sensitivity level plcc44 msl3 ??? , 245 q c (per ipc/jedec j-std-020) human body model class 2 (per jedec standard jesd22-a114) esd machine model class b (per eia/jedec stand ard eia/jesd22-a115) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such requirements. please contact your international rectifier sales repres entative for further information. ??? higher msl ratings may be available for the specific package types listed here. please contact your international rectifier sales repres entative for further information.
www.irf.com 3 irs233(0,2)(d)(s&j)pbf absolute maximum ratings absolute maximum rati ngs indicate sustained limits beyond which dam age to the device may occur. all voltage parameters are absolute voltages referenced to v so . the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v b1,2,3 high side floating supply voltage -0.3 620 v s1,2,3 high side floating offset voltage v b1,2,3 - 20 v b1,2,3 + 0.3 v ho1,2,3 high side floating output voltage v s1,2,3 - 0.3 v b1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 20 v ss logic ground v cc - 20 v cc + 0.3 v lo1,2,3 low side output voltage -0.3 v cc + 0.3 v in _______ ______ logic input voltage ( hin1,2,3, lin1,2,3 & itrip) v ss -0.3 (v ss + 15) or (v cc + 0.3) whichever is lower v flt fault output voltage v ss -0.3 v cc +0.3 v cao operational amplifier output voltage v ss -0.3 v cc +0.3 v ca- operational amplifier inverting input voltage v ss -0.3 v cc +0.3 v dv s /dt allowable offset supply voltage transient ? 50 v/ns (28 lead soic) ? 1.6 p d package power dissipation @ ta
www.irf.com 4 irs233(0,2)(d)(s&j)pbf recommended operating conditions the input/output logic timing diagram is sh own in figure 1. for proper operation t he device should be used within the recommended conditions. all voltage paramet ers are absolute voltage referenced to v so. the v s offset rating is tested with all supplies biased at 15 v differential. note 1: logic operational for v s of (v so -8 v) to (v so +600 v). logic state held for v s of (v so -8 v) to (v so ? v bs ) . note 2: operational for transient neg ative vs of vss - 50 v with a 50 ns pulse width. guaranteed by design. refer to the application information section of this datasheet for more details. note 3: cao input pin is internally clamped with a 5.2 v zener diode. dynamic electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss , c l = 1000 pf, t a = 25 c unless otherwise specified. symbol definition min typ max units test conditions t on turn-on propagation delay 400 500 700 t off turn-off propagation delay 400 500 700 v s1,2,3 = 0 v to 600 v t r turn-on rise time ? 80 125 t f turn-off fall time ? 35 55 v s1,2,3 = 0 v t itrip itrip to output shutdo wn propagation delay 400 660 920 t bl itrip blanking time ? 400 ? t flt itrip to fault indication delay 350 550 870 t flt, in input filter time (all six inputs) ? 325 ? t fltclr lin1,2,3 to fault clear time (2330/2) 5300 8500 13700 1300 2000 3100 dt deadtime: (irs2330(d)) (irs2332(d)) 500 700 1100 ? ? 400 mdt deadtime matching: : (irs2330(d)) (irs2332(d)) ? ? 140 v in = 0 v & 5 v without external deadtime mt delay matching time (t on , t off ) ? ? 50 v in = 0 v & 5 v without external deadtime larger than dt pm pulse width distortion ? ? 75 ns pm input 10 s note: for high side pwm, hin pulse width must be > 1.5 usec symbol definition min. max. units v b1,2,3 high side floating supply voltage v s1,2,3 +10 v s1,2,3 +20 v s1,2,3 static high side floating offset voltage v so -8 (note1) 600 v st1,2,3 transient high side floating offset voltage -50 (note2) 600 v ho1,2,3 high side floating output voltage v s1,2,3 v b1,2,3 v cc low side and logic fixed supply voltage 10 20 v ss logic ground -5 5 v lo1,2,3 low side output voltage 0 v cc v in logic input voltage (hin 1,2,3, lin1,2,3 & itrip) v ss v ss + 5 v flt fault output voltage v ss v cc v cao operational amplifier output voltage v ss v ss + 5 v ca- operational amplifier in verting input voltage v ss v ss + 5 v t a ambient temperature -40 125 c
www.irf.com 5 irs233(0,2)(d)(s&j)pbf dynamic electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss , c l = 1000 pf, t a = 25 c unless otherwise specified. symbol definition min typ max units test conditions sr+ operational amplifier slew rate (+) 5 10 ? sr- operational amplifier slew rate (-) 2.4 3.2 ? v/s 1 v input step
www.irf.com 6 irs233(0,2)(d)(s&j)pbf static electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss and t a = 25 c unless otherwise specified. the v in, v th and i in parameters are referenced to v ss and are applicable to all six logic input leads: hin1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1, 2,3 or lo1,2,3. symbol definition min typ max units test conditions v ih logic ?0? input voltage (out = lo) ? ? 2.2 v il logic ?1? input voltage (out = hi) 0.8 ? ? v v it,th+ itrip input positive going threshold 400 490 580 v oh high level output voltage, v bias - v o ? ? 1000 v in = 0 v, i o = 20 ma v ol low level output voltage, v o ? ? 400 mv v in = 5 v, i o = 20 ma i lk offset supply leakag e current ? ? 50 v b = v s = 600 v i qbs quiescent v bs supply current ? 30 50 a v in = 0 v or 4 v i qcc quiescent v cc supply current ? 4 6.2 ma v in = 0 v i in+ logic ?1? input bias current (out =hi) -400 -300 -100 v in = 0 v i in- logic ?0? input bias current (out = lo) -300 -220 -100 v in = 4 v i itrip+ ?high? itrip bias current ? 5 10 a itrip = 4 v i itrip- ?low? itrip bias current ? ? 30 na itrip = 0 v v bsuv+ v bs supply undervoltage positive going threshold 7.5 8.35 9.2 v bsuv- v bs supply undervoltage negative going threshold 7.1 7.95 8.8 v ccuv+ v cc supply undervoltage positive going threshold 8.3 9 9.7 v ccuv- v cc supply undervoltage negative going threshold 8 8.7 9.4 v ccuvh hysteresis ? 0.3 ? v bsuvh hysteresis ? 0.4 ? v r on, flt fault low on-resistance ? 55 75 ? ? note : the integrated bootstrap diode does not work well with the trapezoidal control.
www.irf.com 7 irs233(0,2)(d)(s&j)pbf static electrical characteristics- continued v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss and t a = 25 c unless otherwise specified. the v in, v th and i in parameters are referenced to v ss and are applicable to all six logic input leads: hin1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1, 2,3 or lo1,2,3. symbol definition min typ max units test conditions i src,amp operational amplifier output source current ? -7 -4 v ca- = 0 v, v so =1 v v cao = 4 v i snk,amp operational amplifier outp ut sink current 1 2.1 ? v ca- = 1 v, v so =0 v v cao = 2 v i o+,amp operational amplifier output high short circuit current -30 -10 ? v ca- = 0 v, v so =5 v v cao = 0 v i o-,amp operational amplifier output low short circuit current ? 4 ? ma v ca- = 5 v, v so =0 v v cao = 5 v functional block diagram note: irs2330 & irs2332 are without integrated bootstrap diode. input signal generator pulse generator level shifter fault logic clear logic under voltage detector input signal generator input signal generator cs pulse generator level shifter pulse generator level shifter driver driver driver driver driver uv detector set reset latch latch uv detector uv detector latch set reset reset set h1 l1 h2 h3 l2 l3 current comparator current amp 0.5v hin1 hin2 hin3 lin1 lin2 lin3 fault itrip cao ca- v cc v ss v b1 v s1 v b2 ho1 ho2 v s2 v b3 ho3 v s3 v so lo1 lo2 lo3 irs2330d/irs2332d integrated bs diode integrated bs diode integrated bs diode driver
www.irf.com 8 irs233(0,2)(d)(s&j)pbf lead definitions symbol description hin1,2,3 logic input for high side gate driver outputs (ho1,2,3), out of phase lin1,2,3 logic input for low side gate driver output (lo1,2,3), out of phase fault indicates over-current or undervoltage lock out (low side) has occurred, negative logic v cc low side and logic fixed supply itrip input for over-current shutdown cao output of current amplifier ca- negative input of current amplifier v ss logic ground v b1,2,3 high side floating supply ho1,2,3 high side ga te drive output v s1,2,3 high side floating supply return lo1,2,3 low side gate drive output v so low side return and positive input of current amplifier lead assignments
www.irf.com 9 irs233(0,2)(d)(s&j)pbf application information and additional details information regarding the following topics are included as subsections within this section of the datasheet. x igbt/mosfet gate drive x switching and timing relationships x deadtime x matched propagation delays x input logic compatibility x undervoltage lockout protection x shoot-through protection x fault reporting x over-current protection x over-temperature shutdown protection x truth table: undervoltage lockout, itrip x advanced input filter x short-pulse / noise rejection x integrated bootstrap functionality x bootstrap power supply design x separate logic and power grounds x negative v s transient soa x dc- bus current sensing x pcb layout tips x additional documentation igbt/mosfet gate drive the irs233(2,0)(d) hvics are designed to drive up to six mosfet or igbt power devices. figures 1 and 2 illustrate several parameters associated with the gate drive functionality of the hvic. the output curr ent of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the high- side power switch and v lo for the low-side power switch; this parameter is sometimes generically called v out and in this case does not differentiate between the high-side or low-side output voltage. figure 1: hvic sourcing current figure 2: hvic sinking current
www.irf.com 10 irs233(0,2)(d)(s&j)pbf switching and timing relationships the relationship between the input and output signals of the irs2 33(0,2)(d) are illustrated below in figures 3. from these figures, we can see the definitions of several timing parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) figure 3: switching time waveforms the following two figures illustrate the timing relationships of so me of the functionality of t he irs233(0,2)(d); this function ality is described in further detail later in this document. during interval a of figure 4, the hvic has received the comm and to turn-on both the high- and low-side switches at the same time; as a result, the shoot-through protecti on of the hvic has prevented this conditio n and both the high- and low-side output are held in the off state. interval b of figures 4 shows that the sign al on the itrip input pin has gone from a low to a high state; as a result, all of t he gate drive outputs have been disabled (i.e., see that hox has return ed to the low state; lox is also held low) and a fault is reported by the fault output transitioning to the low state. once the itrip input has returned to the low state, the fault condition is latched until the all linx become high.
www.irf.com 11 irs233(0,2)(d)(s&j)pbf figure 4: input/output timing diagram deadtime this family of hvics features integrated de adtime protection circuitry. the deadtime for these ics is fixed; other ics within ir?s hvic portfolio feature programmable de adtime for greater design flexibility. the deadtime feature inserts a time period ( a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned off has fully turned off before the second power switch is turned on. this minimum deadtime is automatically inserted whenever the external deadtime is shorter than dt; external de adtimes larger than dt are not modified by the gate driver. figure 5 illustrates the deadtime period and the relationship between the output gate signals. the deadtime circuitry of the irs233(0,2)(d) is matched with re spect to the high- and low-side outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. hinx linx 50% 50% 50% 50% dt dt hox lox figure 5: illustration of deadtime
www.irf.com 12 irs233(0,2)(d)(s&j)pbf matched propagation delays the irs233(0,2)(d) family of hvics is designed with propagatio n delay matching circuitry. with this feature, the ic?s response at the output to a signal at the input r equires approximately the same time duration (i.e., t on , t off ) for both the low- side channels and the high-side channels. additionally, the pr opagation delay for each low-side channel is matched when compared to the other low-side channels and the propagation delays of the high-s ide channels are matched with each other. the propagation turn-on delay (t on ) of the irs233(0,2)(d) is matched to the propagation turn-on delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos a nd ttl outputs. the irs233(0,2)(d) family has been designed to be compatible with 3.3 v and 5 v logic-level signals. the irs233(0,2)(d) features an integr ated 5.2 v zener clamp on the hin, lin, and itrip pins. figur e 6 illustrates an input signal to the irs233(0, 2)(d), its input threshold values, and the logi c state of the ic as a resu lt of the input signal. figure 6: hin & lin input thresholds undervoltage lockout protection this family of ics provides undervo ltage lockout protection on both the v cc (logic and low-side circuitry) power supply and the v bs (high-side circuitry) power supply. figure 7 is used to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/- or v bsuv+/- ) the undervoltage protecti on is enabled or disabled. upon power-up, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turn-on. additionally, if the v cc voltage decreases below the v ccuv- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and shutdown the high- and low-si de gate drive outputs, and the fault pin will transition to the low state to inform the controller of the fault condition. upon power-up, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turn-on. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate drive outputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply voltage is sufficient to fully enhance the power devices. without this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power switch co nducting current while the channel impedance is high; this could result in very high conduction losses within the power device and could lead to power device failure.
www.irf.com 13 irs233(0,2)(d)(s&j)pbf figure 7: uvlo protection shoot-through protection the irs233(0,2)(d) family of high-voltage ics is equipped wi th shoot-through protection circuitry (also known as cross- conduction prevention circuitry). figure 8 shows how this pr otection circuitry prevents both the high- and low-side switches from conducting at the same time. table 1 illustrates the inpu t/output relationship of the devic es in the form of a truth tabl e. note that the irs233(0,2)(d) has inverting inputs (t he output is out-of-phase with its respective input). hin lin ho lo shoot-through protection enabled figure 8: illustration of shoot -through protection circuitry irs233(0,2)(d) hin lin ho lo 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 table 1: input/output truth table
www.irf.com 14 irs233(0,2)(d)(s&j)pbf fault reporting the irs233(0,2)(d) family provides an integrated fault reporting output. there are two situations that would cause the hvic to report a fault via the fault pin. t he first is an undervoltage condition of v cc and the second is if the itrip pin recognizes a fault. once the fault condition occurs, the fault pin is internally pulled to v ss and the fault condition is latched. the fault output stays in the low state until the fault condition has been removed by all linx set to high state. once the fault is remov ed, the voltage on the fault pin will return to v cc . over-current protection the irs233(0,2)(d) hvics are equipped with an itrip input pin. this functionality can be used to detect over-current events in the dc- bus. once the hvic detects an over-current event through the itrip pin, the ou tputs are shutdown, a fault is reported through the fault pin. the level of current at which the over-c urrent protection is initiated is determined by the resistor network (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 9, and the itrip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc- bus and select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the over-current threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc- (r 1 /(r 1 +r 2 )) v cc hin (x3) itrip v ss fault com lin (x 3 ) lo (x3) ho (x3) v b (x3) v s (x3) r 1 r 2 r 0 i dc- figure 9: programming the over-current protection for example, a typical value for resistor r 0 could be 50 m ? over-temperature shutdown protection the itrip input of the irs233(0,2)(d) can also be used to detect over-temperature events in the system and initiate a shutdown of the hvic (and power switches) at that time. in order to use this functionality, the circuit designer will need to design the resistor network as shown in figure 10 an d select the maximum allowable temperature. this network consists of a the rmistor and two standard resistors r 3 and r 4 . as the temperature change s, the resistance of the thermistor will change; this will result in a change of voltage at node v x . the resistor values shou ld be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the maximum allowable temperature is reached. the vo ltage of the itrip pin should not be allowed to exceed 5 v. when using both the over-current protection and over-temper ature protection with the itrip input, or-ing diodes (e.g., dl4148) can be used. this network is shown in figure 11; the or-ing diodes have been labeled d 1 and d 2 .
www.irf.com 15 irs233(0,2)(d)(s&j)pbf figure 10: programming over-temperature protection figure 11: using over-current protection and over-temperature protection truth table: undervoltage lockout and itrip table 2 provides the truth table for the irs233(0, 2)(d). the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gate drive outputs have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance state. the second case shows that the uvlo for v bs has been tripped and that the high-side gate drive outputs have been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receiv es a new falling transition of hin. the third case shows the normal operation of the hvic. the fourth case illustrates that the itrip trip threshold has been reached and that the gate drive ou tputs have been disabled and a fault has been reported through the fault pin. the fault output stays in t he low state until the fault condition has been removed by all linx set to high state. once the faul t is removed, the voltage on t he fault pin will return to v cc . vcc vbs itrip fault lo ho uvlo v cc < v ccuv --- --- 0 0 0 uvlo v bs 15 v < v bsuv 0 v high impedance lin 0 normal operation 15 v 15 v 0 v high impedance lin hin itrip fault 15 v 15 v >v itrip 0 0 0 table 2: irs233(0,2)(d) uvlo, itrip & fault truth table advanced input filter the advanced input filter allows an improvement in the input/ output pulse symmetry of the hvic and helps to reject noise spikes and short pulses. this input filter has been applied to the hin and lin. the wo rking principle of the new filter is sho wn in figures 12 and 13. figure 12 shows a typical input filter an d the asymmetry of the input and output. the upper pair of waveforms (example 1) show an input signal with a duration much longer then t fil,in ; the resulting output is approxim ately the difference between the input signal and t fil,in . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is ap proximately the difference between the input signal and t fil,in . figure 13 shows the advanced input filter and the symmetry between the input and output. the upper pair of waveforms (example 1) show an input signal with a duration much longer then t fil,in ; the resulting output is approximately the same duration as the input signal. the lower pair of waveforms (exa mple 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the same duration as the input signal.
www.irf.com 16 irs233(0,2)(d)(s&j)pbf figure 12: typical input filter figure 13: advanced input filter short-pulse / noise rejection this device?s input filter prov ides protection against short-pulses (e.g., noise ) on the input lines. if the duration of the i nput signal is less than t fil,in , the output will not change states. example 1 of figure 14 shows the input and output in the low state with positive noise spikes of durations less than t fil,in ; the output does not change states. example 2 of figure 19 shows the input and output in the high state with negat ive noise spikes of durations less than t fil,in ; the output does not change states. example 1 example 2 figure 14: noise rejecting input filters figures 15 and 16 present lab data that ill ustrates the characteristics of the input filters while receiving on and off pulses. the input filter characteristic is sh own in figure 15; the left side illustrates the narrow pulse on (short positive pulse) characteristic while the left shows the narrow pulse off (short negative pulse) characteristic. the x-axis of figure 20 shows the duration of pw in , while the y-axis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the input signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the symmetry improving as the duration increases. to ens ure proper operation of the hvic, it is suggested that the input pulse width for th e high-side inputs be
www.irf.com 17 irs233(0,2)(d)(s&j)pbf narrow pulse off 0 200 400 600 800 1000 0 200 400 600 800 1000 time (ns) time (ns) pw out pw in figure 15: irs233(0, 2 )(d) input filter characteristic figure 16: difference between the input pulse and the output pulse integrated bootstrap functionality the new irs233(0,2)d family features integrated high-voltage b ootstrap mosfets that eliminat e the need of the external bootstrap diodes and resistors in many applications. there is one bootstrap mosfet for each high-side ou tput channel and it is connected between the v cc supply and its respective floating supply (i.e., v b1 , v b2 , v b3 ); see figure 17 for an illustration of this internal connection. the integrated bootstrap mo sfet is turned on only during the time when lo is ?high?, and it has a limited source current due to r bs . the v bs voltage will be charged each cycle depending on the on-time of lo and the value of the c bs capacitor, the drain-source (collector-emitter) drop of the external igbt (or mosfet), and the low-side free-wheeling diode drop. the bootstrap mosfet of each channel foll ows the state of the respective low-si de output stage (i.e., the bootstrap mosfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 110% of v cc . in that case, the bootstrap mosfet is designed to remain off until v b returns below that threshold; this concept is illustrated in figure 18.
www.irf.com 18 irs233(0,2)(d)(s&j)pbf figure 17: internal bootstrap mosfet connection figure 18: bootstrap mosfet state diagram a bootstrap mosfet is suitable for most of the pwm modulation schemes and can be used either in parallel with the external bootstrap network (i.e., diode and resistor) or as a replacement of it. the use of the integrated bootstrap as a replacement o f the external bootstrap network may have some limitations. an exam ple of this limitation may arise when this functionality is used in non-complementary pwm schemes (typically 6-step modula tions) and at very high pwm duty cycle. in these cases, superior performances can be achieved by using an external bo otstrap diode in parallel with t he internal bootstrap network. bootstrap power supply design for information related to the design of the bootstrap power supp ly while using the integrated bootstrap functi onality of the irs233(0,2)d family, please refer to application note 1123 (an-1123) entitled ?bootstrap network analysis: focusing on the integrated bootstrap functionality.? this application note is available at www.irf.com . for information related to the design of a standard bootstrap po wer supply (i.e., using an external discrete diode) please refe r to design tip 04-4 (dt04-4) entitled ?using monolithic high voltage gate drivers.? this design tip is available at www.irf.com . separate logic and power grounds the irs233(0,2)(d) has separate logic and power ground pin (v ss and vso respectively) to eliminate some of the noise problems that can occur in power conversion applications. current sensing shunts are commonl y used in many applications for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for motor current measurements. in these situations, it is oft en beneficial to separate the logic and power grounds. figure 19 shows a hvic with separate v ss and vso pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and over-current circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the vso pin is the reference point fo r the low-side gate drive circuitry. the output voltage used to drive the low-side gate is v lo -vso; the gate-emitter voltage (v ge ) of the low-side switch is t he output voltage of the driver minus the drop across r g,lo .
www.irf.com 19 irs233(0,2)(d)(s&j)pbf v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc- bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + - v ge2 + - v ge3 + - itrip v x + - figure 19: separate v ss and vso pins negative v s transient soa a common problem in today?s high-power switching converters is the transient response of the switch node?s voltage as the power switches transition on and off quickly while carrying a lar ge current. a typical 3-phase inverter circuit is shown in fi gure 20; here we define the power switches and diodes of the inverter. if the high-side switch (e.g., the igbt q1 in figures 21 and 22) switches off, while the u phase current is flowing to an inductive load, a current commutation occurs from high-side switch (q1) to the diode (d2) in parallel with the low-side switch of the same inverter leg. at t he same instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 20: three phase inverter
www.irf.com 20 irs233(0,2)(d)(s&j)pbf q1 on d2 v s1 q2 off i u dc+ bus dc- bus dc+ bus q1 off d1 d2 dc- bus v s1 q2 off i u figure 21: q1 conducting figure 22: d2 conducting also when the v phase current flows from the inductive load back to the inverter (see figures 23 and 24), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the negative dc bus voltage. dc+ bus q3 off d3 dc- bus v s2 q4 on i v figure 23: d3 conducting figure 24: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the negative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called ?negative v s transient?. the circuit shown in figure 25 depicts one leg of the three phas e inverter; figures 26 and 27 show a simplified illustration of the commutation of the current between q1 and d2. the parasitic in ductances in the power circuit from the die bonding to the pcb tracks are lumped together in l c and l e for each igbt. when the high-side switch is on, v s1 is below the dc+ voltage by the voltage drops associated with the power switch and t he parasitic elements of the ci rcuit. when the high-side power switch turns off, the load current momentarily flows in the low- side freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this current flows from the dc- bus (whi ch is connected to the vso pin of the hvic) to the load and a negative voltage between v s1 and the dc- bus is induced (i.e., the vso pin of the hvic is at a higher potential than the v s pin).
www.irf.com 21 irs233(0,2)(d)(s&j)pbf figure 25: parasitic elements figure 26: v s positive figure 27: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 3-5 v/ns. the negative v s transient voltage can exceed this range during some events such as short circ uit and over-current shutdown, when di/dt is greater than in normal operation. international rectifier?s hvics have been designed for the robustn ess required in many of today?s demanding applications. an indication of the irs233(0,2)(d)?s robustness can be seen in figure 28, where there is represented the irs233(0,2)(d) safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; viceversa un wanted functional anomalies or permanent damage to the ic do not appear if negative vs transients fall inside soa. at v bs =15v in case of -v s transients greater than -16.5 v for a period of time greater than 50 ns; the hvic will hold by design the high-side outputs in the off state for 4.5 figure 28: negative v s transient soa for irs233(0,2)(d) even though the irs233(0,2)(d) has been shown able to handle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use.
www.irf.com 22 irs233(0,2)(d)(s&j)pbf dc- bus current sensing a ground referenced current signal amplifier has been included so that the current in the return leg of the dc bus may be monitored. a typical circuit configuration is provided in fig.29. the signal coming from the shunt resistor is amplified by the ratio (r1+r2)/r2. additional details can be found on de sign tip dt 92-6. this design tip is available at www.irf.com . figure 29: current amplifier typical configuration in the following figures 30, 31, 32, 33 the configurations used to meas ure the operational amplifier characteristics are shown. v cc cao v so ca - v ss 15v + 1k 20 k 0.2v v so v so 21 - 0.2v figure 30: operational amplifier slew rate measurement figure 31: operational amplifier input offset voltage measurement
www.irf.com 23 irs233(0,2)(d)(s&j)pbf figure 32: operational amplifier common mode rejection measurement figure 33: operational amplifier power supply rejection measurement pcb layout tips distance between high and low voltage components: it?s strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of th e device. the irs233(0,2)(d) in the plcc44 package has had some unused pins removed in order to maximize t he distance between the high voltage and low voltage pins. please see the case outline plcc44 information in this datasheet for the details. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to rece ive and transmit em noise (see figure 34). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate dr ive loops must be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector-to-gate parasitic capacitance. the parasitic auto-ind uctance of the gate loop contri butes to developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect. figure 34: antenna loops
www.irf.com 24 irs233(0,2)(d)(s&j)pbf supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 35. a ceramic 1 v cc hin (x3) itrip v ss fault com lin (x 3 ) lo (x3) ho (x3) v b (x3) v s (x3) r 1 i rs233(0,2)(d) r 2 r 0 i dc- figure 35: supply capacitor routing and placement : power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the high-side emitter to low-side collector di stance, and 2) minimize the low-side emitter to negative bus rail stray inductance. however, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes placing a resistor (5 ? figure 36: v s resistor figure 37: v s clamping diode additional documentation several technical documents related to the use of hvics are available at www.irf.com ; use the site search function and the document number to quickly locate them. belo w is a short list of some of these documents. dt97-3: managing transients in control ic driven power stages an-1123: bootstrap network analysis: focusing on the integrated bootstrap functionality dt04-4: using monolithic high voltage gate drivers an-978: hv floating mos-gate driver ics
www.irf.com 25 irs233(0,2)(d)(s&j)pbf parameter temperature trends figures 38-76 provide information on the ex perimental performance of the irs233(0,2)(d)(s&j) hvic. the line plotted in each figure is generated from actual lab data. a small number of individual samples were tested at three temperatures (-40 oc, 25 oc , and 125 oc) in order to generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data p oint at each of the tested temperatur es) that have been connected together to illust rate the understood tem perature trend. the individual data points on the curve were det ermined by calculating the averaged experim ental value of the par ameter (for a give n temperature). 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 temperature ( o c) t on (ns) exp . fig. 38. turn-on propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 temperature ( o c) t on (ns) exp . fig. 39. turn-on propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 -50-250 255075100125 temperature ( o c) t off (ns) exp . fig. 40. turn-off propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 -50-250 255075100125 temperature ( o c) t off (ns) exp . fig. 41. turn-off propagation delay vs. temperature
www.irf.com 26 irs233(0,2)(d)(s&j)pbf 0 20 40 60 80 100 120 140 160 180 200 -50-250 255075100125 temperature ( o c) t r (ns) exp . fig. 42. turn-on rise time vs. temperature 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) t f (ns) exp . fig.43. turn-off fall time vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) t itrip (ns) exp . fig. 44. itrip to output shutdown propagation dela y vs. tem p erature 0 100 200 300 400 500 600 700 800 900 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) t flt (ns) exp . fig. 45. itrip to fault indication delay vs. temperature 0 2000 4000 6000 8000 10000 12000 14000 16000 -50-25 0 25 50 75100125 temperature ( o c) tfltclr (ns) exp . fig.46. fault clear time vs. temperature 0 200 400 600 800 1000 1200 -50-250 255075100125 temperature ( o c) dlton1 (ns) exp . fig. 47. dead time vs. temperature
www.irf.com 27 irs233(0,2)(d)(s&j)pbf 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) sr+_amp (v/us) exp. fig. 48. operational amplifier slew rate (+) vs. temperature 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature ( o c) sr-_amp (v/us) exp . fig. 49. operational amplifier slew rate (-) vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 -50 -25 0 25 50 75 100 125 temperature ( o c) lin1_vth+ (v) exp. fig. 50. input positive going threshold vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 -50 -25 0 25 50 75 100 125 temperature ( o c) lin1_vth- (v) exp. fig. 51. input negative going threshold vs. tem p erature 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 temperature ( o c) v it,th+ (mv) ex p. fig. 52. itrip input positive going threshold vs. temperature 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 temperature ( o c) v it,th- (mv) exp. fig. 53. itrip input negative going threshold vs. temperature
www.irf.com 28 irs233(0,2)(d)(s&j)pbf 0 50 100 150 200 250 300 350 400 450 -50-25 0 255075100125 temperature ( o c) vol_lo1 (mv) exp . fig. 54. low level output voltage vs. temperature 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) ileak1_vccmax (a) exp . fig. 55. offset supply leakage current vs. temperature 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 temperature ( o c) i qcc1 (ma) exp . fig. 56. quiescent v cc supply current vs. tem p erature 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 temperature ( o c) i qcc0 (ma) exp . fig. 57. quiescent v cc supply current vs. tem p erature 0 10 20 30 40 50 60 70 80 -50-25 0 255075100125 temperature ( o c) i qbs10 ( a) exp . fig. 58. quiescent v bs supply current vs. temperature 0 10 20 30 40 50 60 70 80 -50-25 0 255075100125 temperature ( o c) i qbs11 ( a) exp. fig. 59. quiescent v bs supply current vs. temperature
www.irf.com 29 irs233(0,2)(d)(s&j)pbf 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv- (v) exp. fig. 60. v cc supply undervoltage negative going threshold vs. temperature 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 -50 -25 0 25 50 75 100 125 temperature ( o c) v ccuv+ (v) exp . fig. 61. v cc supply undervoltage positive going threshold vs. temperature 6.0 6.5 7.0 7.5 8.0 8.5 9.0 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv- (v) exp . fig. 62. v bs supply undervoltage negative going threshold vs. temperature 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 -50 -25 0 25 50 75 100 125 temperature ( o c) v bsuv+ (v) exp. fig. 63. v bs supply undervoltage positive going threshold vs. temperature 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 temperature ( o c) r on,flt ( ? ) exp . fig. 64. fault low on-resistance vs. temperature -450 -400 -350 -300 -250 -200 -150 -100 -50 0 -50 -25 0 25 50 75 100 125 temperature ( o c) i o+ (ma) exp . fig. 65. output high short circuit pulsed current vs. temperature
www.irf.com 30 irs233(0,2)(d)(s&j)pbf 6 106 206 306 406 506 606 706 -50 -25 0 25 50 75 100 125 temperature ( o c) i o- (ma) exp . fig. 66. output low short circuit pulsed current vs. temperature -20 -15 -10 -5 0 5 10 15 20 -50 -25 0 25 50 75 100 125 temperature ( o c) vos_amp (mv) exp . fig. 67. offset opamp vs. temperature 0 20 40 60 80 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 temperature ( o c) psrr_amp (db) exp. fig. 68. operational amplifier power supply re j ection ratio vs. temperature 0 20 40 60 80 100 120 140 160 180 200 -50 -25 0 25 50 75 100 125 temperature ( o c) cmrr_amp (db) exp. fig. 69. operational amplifier common mode re j ection ratio vs. temperature 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 -50 -25 0 25 50 75 100 125 temperature ( o c) voh_amp (v) exp . fig. 70. operational amplifier high level output voltage vs. temperature 0 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 temperature ( o c) voh_amp (mv) exp . fig. 71. operational amplifier low level output voltage vs. temperature
www.irf.com 31 irs233(0,2)(d)(s&j)pbf 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature ( o c) isnk_amp (ma) exp . fig. 72. operational amplifier output sink current vs. temperature 0 2 4 6 8 10 12 14 16 -50 -25 0 25 50 75 100 125 temperature ( o c) io-_amp (ma) exp. fig. 73. operational amplifier output low short circuit current vs. temperature -16 -14 -12 -10 -8 -6 -4 -2 0 -50 -25 0 25 50 75 100 125 temperature ( o c) isrc_amp (ma) exp. fig. 74. operational amplifier output source current vs. temperature -35 -30 -25 -20 -15 -10 -5 0 -50 -25 0 25 50 75 100 125 temperature ( o c) io+_amp (ma) exp . fig. 75. operational amplifier output high short circuit current vs. temperature -14 -12 -10 -8 -6 -4 -2 0 -50 -25 0 25 50 75 100 125 temperature ( o c) vs1_rst_domin (v) exp . fig. 76. max ?vs vs. temperature
www.irf.com 32 irs233(0,2)(d)(s&j)pbf case outlines
www.irf.com 33 irs233(0,2)(d)(s&j)pbf case outlines
www.irf.com 34 irs233(0,2)(d)(s&j)pbf tape and reel details: soic28w carrier tape dimension for 28soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 23.70 24.30 0.933 0.956 d 11.40 11.60 0.448 0.456 e 10.80 11.00 0.425 0.433 f 18.20 18.40 0.716 0.724 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 28soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 30.40 n/a 1.196 g 26.50 29.10 1.04 1.145 h 24.40 26.40 0.96 1.039 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c
www.irf.com 35 irs233(0,2)(d)(s&j)pbf tape and reel details: plcc44 carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c
www.irf.com 36 irs233(0,2)(d)(s&j)pbf ordering information standard pack base part number package type form quantity complete part number tube/bulk 25 irs233(0,2)(d)spbf soic28w tape and reel 1000 irs233(0,2)(d)strpbf tube/bulk 27 irs233(0,2)(d)jpbf irs233(0,2)(d) plcc44 tape and reel 500 irs233(0,2)(d)jtrpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this in formation. international rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this in formation. no license is granted by implication or otherwise u nder any patent or patent rights of international rectifier. the specifications mentioned in this doc ument are subject to change without notice. this document supersedes and replaces all inform ation previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105

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